View M29F800DT06_1269225.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

M29F800DT M29F800DB
8 Mbit (1Mb x8 or 512Kb x16, Boot Block) 5V Supply Flash Memory
Feature summary
Supply voltage - VCC = 5V 10% for Program, Erase and Read Access time: 55, 70, 90ns Programming time - 10s per Byte/Word typical 19 Memory Blocks - 1 Boot Block (Top or Bottom location) - 2 Parameter and 16 Main Blocks Program/Erase controller - Embedded Byte/Word Program algorithms Erase Suspend and Resume modes - Read and Program another Block during Erase Suspend Unlock Bypass Program command - Faster Production/batch Programming Temporary Block Unprotection mode Common Flash Interface - 64 bit Security Code Low power consumption - Standby and Automatic Standby 100,000 Program/Erase cycles per Block Electronic Signature - Manufacturer Code: 0020h - Top Device Code M29F800DT: 22ECh - Bottom Device Code M29F800DB: 2258h TSOP48 (N) 12 x 20mm

SO44 (M)

August 2006
Rev 5
1/53
www.st.com 1
Contents
M29F800DT
Contents
1 2 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.0.1 2.0.2 2.0.3 2.0.4 2.0.5 2.0.6 2.0.7 2.0.8 2.0.9 2.0.10 2.0.11 2.0.12 Address Inputs (A0-A18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Data Inputs/Outputs (DQ0-DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Data Inputs/Outputs (DQ8-DQ14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Data Input/Output or Address Input (DQ15A-1) . . . . . . . . . . . . . . . . . . . 12 Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Reset/Block Temporary Unprotect (RP) . . . . . . . . . . . . . . . . . . . . . . . . . 13 Ready/Busy output (RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Byte/Word Organization Select (BYTE) . . . . . . . . . . . . . . . . . . . . . . . . . 13 VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 VSS Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3
Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.0.1 3.0.2 3.0.3 3.0.4 3.0.5 3.0.6 3.0.7 3.0.8 Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Automatic Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Special bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Block Protection and Blocks Unprotection . . . . . . . . . . . . . . . . . . . . . . . 15
4
Command Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.0.1 4.0.2 4.0.3 4.0.4 4.0.5 4.0.6 4.0.7 4.0.8 Read/Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Auto Select command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Unlock Bypass command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Unlock Bypass Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Unlock Bypass Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Chip Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2/53
M29F800DT 4.0.9 4.0.10 4.0.11 4.0.12
Contents Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Read CFI Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Block Protect and Chip Unprotect commands . . . . . . . . . . . . . . . . . . . . 19
5
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.0.1 5.0.2 5.0.3 5.0.4 5.0.5 Data Polling Bit (DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Toggle Bit (DQ6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Error Bit (DQ5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Erase Timer Bit (DQ3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Alternative Toggle Bit (DQ2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6 7 8 9
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Appendix A Block address table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Appendix B Common Flash Interface (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Appendix C Block protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.1 9.2 Programmer technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 In-System technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3/53
List of tables
M29F800DT
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Bus operations, BYTE = VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Bus operations, BYTE = VIH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Commands, 16-bit mode, BYTE = VIH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Commands, 8-bit mode, BYTE = VIL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Program, Erase times and Program, Erase Endurance cycles. . . . . . . . . . . . . . . . . . . . . . 21 Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Write AC characteristics, Write Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Write AC characteristics, Chip Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Reset/Block Temporary Unprotect AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 SO44 - 44 lead Plastic Small Outline, 525 mils body width, package mechanical data. . . 36 TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, package mechanical data . . . 37 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Top Boot Block addresses, M29F800D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Bottom Boot Block addresses, M29F800DB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Primary Algorithm-specific Extended Query table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Security Code Area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Programmer technique bus operations, BYTE = VIH or VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4/53
M29F800DT
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 SO connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 TSOP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Block addresses (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Block addresses (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Data Polling flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Data Toggle flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 AC measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Read Mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Write AC waveforms, Write Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Write AC waveforms, Chip Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Reset/Block Temporary Unprotect AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 SO44 - 44 lead Plastic Small Outline, 525 mils body width, package outline . . . . . . . . . . . 36 TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, package outline . . . . . . . . . . . 37 Programmer Equipment Block Protect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Programmer Equipment Chip Unprotect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 In-System Equipment Block Protect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 In-System Equipment Chip Unprotect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5/53
Summary description
M29F800DT
1
Summary description
The M29F800D is a 8 Mbit (1Mb x8 or 512Kb x16) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single low voltage (5V) supply. On power-up the memory defaults to its Read mode where it can be read in the same way as a ROM or EPROM. The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. Each block can be protected independently to prevent accidental Program or Erase commands from modifying the memory. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards. The blocks in the memory are asymmetrically arranged, see Figure 4: Block addresses (x8), and Figure 5: Block addresses (x16). The first or last 64 Kbytes have been divided into four additional blocks. The 16 Kbyte Boot Block can be used for small initialization code to start the microprocessor, the two 8 Kbyte Parameter Blocks can be used for parameter storage and the remaining 32K is a small Main Block where the application may be stored. Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory. They allow simple connection to most microprocessors, often without additional logic. The memory is offered in SO44 and TSOP48 (12 x 20mm) packages. The memory is supplied with all the bits erased (set to '1').
6/53
M29F800DT Figure 1. Logic diagram
Summary description
VCC
19 A0-A18 W E G RP BYTE M29F800DT M29F800DB
15 DQ0-DQ14 DQ15A-1
RB
VSS
AI06148B
Table 1.
A0-A18 DQ0-DQ7 DQ8-DQ14 DQ15A-1 E G W RP RB BYTE VCC VSS NC
Signal names
Address Inputs Data Inputs/Outputs Data Inputs/Outputs Data Input/Output or address Input Chip Enable Output Enable Write Enable Reset/Block Temporary Unprotect Ready/Busy Output Byte/Word Organization Select Supply voltage Ground Not Connected Internally
7/53
Summary description Figure 2. SO connections
M29F800DT
RB A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 E VSS G DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11
1 44 2 43 3 42 4 41 5 40 6 39 7 38 8 37 9 36 10 35 11 M29F800DT 34 12 M29F800DB 33 13 32 14 31 15 30 16 29 28 17 27 18 26 19 25 20 21 24 22 23
RP W A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE VSS DQ15A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC
AI06150
8/53
M29F800DT Figure 3. TSOP connections
Summary description
A15 A14 A13 A12 A11 A10 A9 A8 NC NC W RP NC NC RB A18 A17 A7 A6 A5 A4 A3 A2 A1
1
48
12 13
M29F800DT M29F800DB
37 36
24
25
A16 BYTE VSS DQ15A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 G VSS E A0
AI06149
9/53
Summary description Figure 4. Block addresses (x8)
M29F800DT
M29F800DT Top Boot Block Addresses (x8)
M29F800DB Bottom Boot Block Addresses (x8)
FFFFFh 16 KByte FC000h FBFFFh 8 KByte FA000h F9FFFh 8 KByte F8000h F7FFFh 32 KByte F0000h EFFFFh 64 KByte E0000h
FFFFFh 64 KByte F0000h EFFFFh 64 KByte E0000h Total of 15 64 KByte Blocks
1FFFFh 64 KByte 10000h 0FFFFh 32 KByte Total of 15 64 KByte Blocks 08000h 07FFFh 8 KByte 06000h 05FFFh 8 KByte 04000h 03FFFh 16 KByte 00000h
1FFFFh 64 KByte 10000h 0FFFFh 64 KByte 00000h
1. Also see Appendix A, Table 19, and Table 20 for a full listing of the Block addresses.
10/53
M29F800DT Figure 5. Block addresses (x16)
Summary description
M29F800DT Top Boot Block Addresses (x16)
M29F800DB Bottom Boot Block Addresses (x16)
7FFFFh 8 KWord 7E000h 7DFFFh 4 KWord 7D000h 7CFFFh 4 KWord 7C000h 7BFFFh 16 KWord 78000h 77FFFh 32 KWord 70000h
7FFFFh 32 KWord 78000h 77FFFh 32 KWord 70000h Total of 15 32 KWord Blocks
0FFFFh 32 KWord 08000h 07FFFh 16 KWord Total of 15 32 KWord Blocks 04000h 03FFFh 4 KWord 03000h 02FFFh 4 KWord 02000h 01FFFh 8 KWord 00000h
0FFFFh 32 KWord 08000h 07FFFh 32 KWord 00000h
1. Also see Appendix A, Table 19, and Table 20 for a full listing of the Block addresses.
11/53
Signal descriptions
M29F800DT
2
Signal descriptions
See Figure 1: Logic diagram, and Table 1: Signal names for a brief overview of the signals connected to this device.
2.0.1
Address Inputs (A0-A18)
The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine.
2.0.2
Data Inputs/Outputs (DQ0-DQ7)
The Data Inputs/Outputs output the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands sent to the Command Interface of the internal state machine.
2.0.3
Data Inputs/Outputs (DQ8-DQ14)
The Data Inputs/Outputs output the data stored at the selected address during a Bus Read operation when BYTE is High, VIH. When BYTE is Low, VIL, these pins are not used and are high impedance. During Bus Write operations the Command Register does not use these bits. When reading the Status Register these bits should be ignored.
2.0.4
Data Input/Output or Address Input (DQ15A-1)
When BYTE is High, VIH, this pin behaves as a Data Input/Output pin (as DQ8-DQ14). When BYTE is Low, VIL, this pin behaves as an address pin; DQ15A-1 Low will select the LSB of the Word on the other addresses, DQ15A-1 High will select the MSB. Throughout the text consider references to the Data Input/Output to include this pin when BYTE is High and references to the Address Inputs to include this pin when BYTE is Low except when stated explicitly otherwise.
2.0.5
Chip Enable (E)
The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write operations to be performed. When Chip Enable is High, VIH, all other pins are ignored.
2.0.6
Output Enable (G)
The Output Enable, G, controls the Bus Read operation of the memory.
2.0.7
Write Enable (W)
The Write Enable, W, controls the Bus Write operation of the memory's Command Interface.
12/53
M29F800DT
Signal descriptions
2.0.8
Reset/Block Temporary Unprotect (RP)
The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the memory or to temporarily unprotect all Blocks that have been protected. A Hardware Reset is achieved by holding Reset/Block Temporary Unprotect Low, VIL, for at least tPLPX. After Reset/Block Temporary Unprotect goes High, VIH, the memory will be ready for Bus Read and Bus Write operations after tPHEL or tRHEL, whichever occurs last. See Section 2.0.9: Ready/Busy output (RB), Table 15: Reset/Block Temporary Unprotect AC characteristics, and Figure 13: Reset/Block Temporary Unprotect AC waveforms for more details. Holding RP at VID will temporarily unprotect the protected Blocks in the memory. Program and Erase operations on all blocks will be possible. The transition from VIH to VID must be slower than tPHPHH.
2.0.9
Ready/Busy output (RB)
The Ready/Busy pin is an open-drain output that can be used to identify when the device is performing a Program or Erase operation. During Program or Erase operations Ready/Busy is Low, VOL. Ready/Busy is high-impedance during Read mode, Auto Select mode and Erase Suspend mode. After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy becomes high-impedance. See Table 15: Reset/Block Temporary Unprotect AC characteristics, and Figure 13: Reset/Block Temporary Unprotect AC waveforms. The use of an open-drain output allows the Ready/Busy pins from several memories to be connected to a single pull-up resistor. A Low will then indicate that one, or more, of the memories is busy.
2.0.10
Byte/Word Organization Select (BYTE)
The Byte/Word Organization Select pin is used to switch between the 8-bit and 16-bit Bus modes of the memory. When Byte/Word Organization Select is Low, VIL, the memory is in 8bit mode, when it is High, VIH, the memory is in 16-bit mode.
2.0.11
VCC Supply Voltage
The VCC Supply Voltage supplies the power for all operations (Read, Program, Erase etc.). The Command Interface is disabled when the VCC Supply Voltage is less than the Lockout voltage, VLKO. This prevents Bus Write operations from accidentally damaging the data during power up, power down and power surges. If the Program/Erase Controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid. A 0.1F capacitor should be connected between the VCC Supply Voltage pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations, ICC3.
2.0.12
VSS Ground
The VSS Ground is the reference for all voltage measurements.
13/53
Bus operations
M29F800DT
3
Bus operations
There are five standard bus operations that control the device. These are Bus Read, Bus Write, Output Disable, Standby and Automatic Standby. See Table 2: Bus operations, BYTE = VIL, and Table 3: Bus operations, BYTE = VIH for a summary. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus operations.
3.0.1
Bus Read
Bus Read operations read from the memory cells, or specific registers in the Command Interface. A valid Bus Read operation involves setting the desired address on the Address Inputs, applying a Low signal, VIL, to Chip Enable and Output Enable and keeping Write Enable High, VIH. The Data Inputs/Outputs will output the value, see Figure 10: Read Mode AC waveforms, and Table 12: Read AC characteristics for details of when the output becomes valid.
3.0.2
Bus Write
Bus Write operations write to the Command Interface. A valid Bus Write operation begins by setting the desired address on the Address Inputs. The Address Inputs are latched by the Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs last. The Data Inputs/Outputs are latched by the Command Interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, VIH, during the whole Bus Write operation. See Figure 11: Write AC waveforms, Write Enable controlled, Figure 12: Write AC waveforms, Chip Enable controlled, Table 13: Write AC characteristics, Write Enable controlled, and Table 14: Write AC characteristics, Chip Enable controlled, for details of the timing requirements.
3.0.3
Output Disable
The Data Inputs/Outputs are in the high impedance state when Output Enable is High, VIH.
3.0.4
Standby
When Chip Enable is High, VIH, the memory enters Standby mode and the Data Inputs/Outputs pins are placed in the high-impedance state. To reduce the Supply Current to the Standby Supply Current, ICC2, Chip Enable should be held within VCC 0.2V. For the Standby current level see Table 11: DC characteristics. During program or erase operations the memory will continue to use the Program/Erase Supply Current, ICC3, for Program or Erase operations until the operation completes.
3.0.5
Automatic Standby
If CMOS levels (VCC 0.2V) are used to drive the bus and the bus is inactive for 150ns or more the memory enters Automatic Standby where the internal Supply Current is reduced to the Standby Supply Current, ICC2. The Data Inputs/Outputs will still output data if a Bus Read operation is in progress.
14/53
M29F800DT
Bus operations
3.0.6
Special bus operations
Additional bus operations can be performed to read the Electronic Signature and also to apply and remove Block Protection. These bus operations are intended for use by programming equipment and are not usually used in applications. They require VID to be applied to some pins.
3.0.7
Electronic Signature
The memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. These codes can be read by applying the signals listed in Table 2: Bus operations, BYTE = VIL, and Table 3: Bus operations, BYTE = VIH.
3.0.8
Block Protection and Blocks Unprotection
Each block can be separately protected against accidental Program or Erase. Protected blocks can be unprotected to allow data to be changed. There are two methods available for protecting and unprotecting the blocks, one for use on programming equipment and the other for in-system use. Block Protect and Chip Unprotect operations are described in Appendix C. Table 2. Bus operations, BYTE = VIL(1)
E VIL VIL X VIH VIL VIL G VIL VIH VIH X VIL VIL W VIH VIL VIH X VIH VIH Address Inputs DQ15A-1, A0-A18 Cell address Command address X X A0 = VIL, A1 = VIL, A9 = VID, Others VIL or VIH A0 = VIH, A1 = VIL, A9 = VID, Others VIL or VIH Data Inputs/Outputs DQ14-DQ8 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z DQ7-DQ0 Data Output Data Input Hi-Z Hi-Z 20h ECh (M29F800DT) 58h (M29F800DB)
Operation Bus Read Bus Write Output Disable Standby Read Manufacturer Code Read Device Code
1. X = VIL or VIH.
Table 3.
Bus operations, BYTE = VIH(1)
Operation E VIL VIL X VIH VIL VIL G VIL VIH VIH X VIL VIL W VIH VIL VIH X VIH VIH Address Inputs A0-A18 Cell address Command address X X A0 = VIL, A1 = VIL, A9 = VID, Others VIL or VIH A0 = VIH, A1 = VIL, A9 = VID, Others VIL or VIH Data Inputs/Outputs DQ15A-1, DQ14-DQ0 Data Output Data Input Hi-Z Hi-Z 0020h 22ECh (M29F800DT) 2258h (M29F800DB)
Bus Read Bus Write Output Disable Standby Read Manufacturer Code Read Device Code
1. X = VIL or VIH.
15/53
Command Interface
M29F800DT
4
Command Interface
All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. Failure to observe a valid sequence of Bus Write operations will result in the memory returning to Read mode. The long command sequences are imposed to maximize data security. The address used for the commands changes depending on whether the memory is in 16bit or 8-bit mode. See either Table 4, or Table 5, depending on the configuration that is being used, for a summary of the commands.
4.0.1
Read/Reset command
The Read/Reset command returns the memory to its Read mode where it behaves like a ROM or EPROM, unless otherwise stated. It also resets the errors in the Status Register. Either one or three Bus Write operations can be used to issue the Read/Reset command. The Read/Reset Command can be issued, between Bus Write cycles before the start of a program or erase operation, to return the device to read mode. Once the program or erase operation has started the Read/Reset command is no longer accepted. The Read/Reset command will not abort an Erase operation when issued while in Erase Suspend.
4.0.2
Auto Select command
The Auto Select command is used to read the Manufacturer Code, the Device Code and the Block Protection Status. Three consecutive Bus Write operations are required to issue the Auto Select command. Once the Auto Select command is issued the memory remains in Auto Select mode until a Read/Reset command is issued. Read CFI Query and Read/Reset commands are accepted in Auto Select mode, all other commands are ignored. From the Auto Select mode the Manufacturer Code can be read using a Bus Read operation with A0 = VIL and A1 = VIL. The other address bits may be set to either VIL or VIH. The Manufacturer Code for STMicroelectronics is 0020h. The Device Code can be read using a Bus Read operation with A0 = VIH and A1 = VIL. The other address bits may be set to either VIL or VIH. The Block Protection Status of each block can be read using a Bus Read operation with A0 = VIL, A1 = VIH, and A12-A18 specifying the address of the block. The other address bits may be set to either VIL or VIH. If the addressed block is protected then 01h is output on Data Inputs/Outputs DQ0-DQ7, otherwise 00h is output.
16/53
M29F800DT
Command Interface
4.0.3
Program command
The Program command can be used to program a value to one address in the memory array at a time. The command requires four Bus Write operations, the final write operation latches the address and data in the internal state machine and starts the Program/Erase Controller. If the address falls in a protected block then the Program command is ignored, the data remains unchanged. The Status Register is never read and no error condition is given. During the program operation the memory will ignore all commands. It is not possible to issue any command to abort or pause the operation. Typical program times are given in Table 6: Program, Erase times and Program, Erase Endurance cycles. Bus Read operations during the program operation will output the Status Register on the Data Inputs/Outputs. See Section 5: Status Register, for more details. After the program operation has completed the memory will return to the Read mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. Note that the Program command cannot change a bit set at '0' back to '1'. One of the Erase Commands must be used to set all the bits in a block or in the whole memory from '0' to '1'.
4.0.4
Unlock Bypass command
The Unlock Bypass command is used in conjunction with the Unlock Bypass Program command to program the memory. When the access time to the device is long (as with some EPROM programmers) considerable time saving can be made by using these commands. Three Bus Write operations are required to issue the Unlock Bypass command. Once the Unlock Bypass command has been issued the memory will only accept the Unlock Bypass Program command and the Unlock Bypass Reset command. The memory can be read as if in Read mode.
4.0.5
Unlock Bypass Program command
The Unlock Bypass Program command can be used to program one address in memory at a time. The command requires two Bus Write operations, the final write operation latches the address and data in the internal state machine and starts the Program/Erase Controller. The Program operation using the Unlock Bypass Program command behaves identically to the Program operation using the Program command. A protected block cannot be programmed; the operation cannot be aborted and the Status Register is read. Errors must be reset using the Read/Reset command, which leaves the device in Unlock Bypass Mode. See the Program command for details on the behavior.
4.0.6
Unlock Bypass Reset command
The Unlock Bypass Reset command can be used to return to Read/Reset mode from Unlock Bypass Mode. Two Bus Write operations are required to issue the Unlock Bypass Reset command. Read/Reset command does not exit from Unlock Bypass Mode.
17/53
Command Interface
M29F800DT
4.0.7
Chip Erase command
The Chip Erase command can be used to erase the entire chip. Six Bus Write operations are required to issue the Chip Erase Command and start the Program/Erase Controller. If any blocks are protected then these are ignored and all the other blocks are erased. If all of the blocks are protected the Chip Erase operation appears to start but will terminate within about 100s, leaving the data unchanged. No error condition is given when protected blocks are ignored. During the erase operation the memory will ignore all commands. It is not possible to issue any command to abort the operation. Typical chip erase times are given in Table 6. All Bus Read operations during the Chip Erase operation will output the Status Register on the Data Inputs/Outputs. See Section 5: Status Register, for more details. After the Chip Erase operation has completed the memory will return to the Read Mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read Mode. The Chip Erase Command sets all of the bits in unprotected blocks of the memory to '1'. All previous data is lost.
4.0.8
Block Erase command
The Block Erase command can be used to erase a list of one or more blocks. Six Bus Write operations are required to select the first block in the list. Each additional block in the list can be selected by repeating the sixth Bus Write operation using the address of the additional block. The Block Erase operation starts the Program/Erase Controller about 50s after the last Bus Write operation. Once the Program/Erase Controller starts it is not possible to select any more blocks. Each additional block must therefore be selected within 50s of the last block. The 50s timer restarts when an additional block is selected. The Status Register can be read after the sixth Bus Write operation. See the Status Register for details on how to identify if the Program/Erase Controller has started the Block Erase operation. If any selected blocks are protected then these are ignored and all the other selected blocks are erased. If all of the selected blocks are protected the Block Erase operation appears to start but will terminate within about 100s, leaving the data unchanged. No error condition is given when protected blocks are ignored. During the Block Erase operation the memory will ignore all commands except the Erase Suspend command. Typical block erase times are given in Table 6. All Bus Read operations during the Block Erase operation will output the Status Register on the Data Inputs/Outputs. See Section 5: Status Register, for more details. After the Block Erase operation has completed the memory will return to the Read Mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. The Block Erase Command sets all of the bits in the unprotected selected blocks to '1'. All previous data in the selected blocks is lost.
18/53
M29F800DT
Command Interface
4.0.9
Erase Suspend command
The Erase Suspend command may be used to temporarily suspend a Block Erase operation and return the memory to Read mode. The command requires one Bus Write operation. The Program/Erase Controller will suspend within the Erase Suspend Latency Time (refer to Table 6 for value) of the Erase Suspend command being issued. Once the Program/Erase Controller has stopped the memory will be set to Read mode and the Erase will be suspended. If the Erase Suspend command is issued during the period when the memory is waiting for an additional block (before the Program/Erase Controller starts) then the Erase is suspended immediately and will start immediately when the Erase Resume command is issued. It is not possible to select any further blocks to erase after the Erase Resume. During Erase Suspend it is possible to Read and Program cells in blocks that are not being erased; both Read and Program operations behave as normal on these blocks. If any attempt is made to program in a protected block or in the suspended block then the Program command is ignored and the data remains unchanged. The Status Register is not read and no error condition is given. Reading from blocks that are being erased will output the Status Register. It is also possible to issue the Auto Select, Read CFI Query and Unlock Bypass commands during an Erase Suspend. The Read/Reset command must be issued to return the device to Read Array mode before the Resume command will be accepted.
4.0.10
Erase Resume command
The Erase Resume command must be used to restart the Program/Erase Controller from Erase Suspend. An erase can be suspended and resumed more than once.
4.0.11
Read CFI Query command
The Read CFI Query Command is used to read data from the Common Flash Interface (CFI) Memory Area. This command is valid when the device is ready to read the array data or when the device is in autoselected mode. One Bus Write cycle is required to issue the Read CFI Query Command. Once the command is issued subsequent Bus Read operations read from the Common Flash Interface Memory Area. The Read/Reset command must be issued to return the device to Read Array mode. See Appendix B, Table 21, Table 22, Table 23, Table 24, Table 25, and Appendix B: Common Flash Interface (CFI), for details on the information contained in the Common Flash Interface (CFI) memory area.
4.0.12
Block Protect and Chip Unprotect commands
Each block can be separately protected against accidental Program or Erase. The whole chip can be unprotected to allow the data inside the blocks to be changed. Block Protect and Chip Unprotect operations are described in Appendix C.
19/53
Command Interface Table 4. Commands, 16-bit mode, BYTE = VIH(1)
Bus Write operations Length Command 1st 2nd 3rd 4th 5th
M29F800DT
6th
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data 1 Read/Reset 3 Auto Select Program Unlock Bypass Unlock Bypass Program Unlock Bypass Reset Chip Erase Block Erase Erase Suspend Erase Resume Read CFI Query 3 4 3 2 2 6 6+ 1 1 1 555 555 555 555 X X 555 555 X X 55 AA AA AA AA A0 90 AA AA B0 30 98 2AA 2AA 2AA 2AA PA X 2AA 2AA 55 55 55 55 PD 00 55 55 555 555 80 80 555 555 AA AA 2AA 2AA 55 55 555 BA 10 30 X 555 555 555 F0 90 A0 20 PA PD X F0
1. X Don't Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal. The Command Interface only uses A-1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A18, DQ8DQ14 and DQ15 are Don't Care. DQ15A-1 is A-1 when BYTE is VIL or DQ15 when BYTE is VIH.
20/53
M29F800DT Table 5. Commands, 8-bit mode, BYTE = VIL(1)
Bus Write operations Length Command 1st 2nd 3rd 4th
Command Interface
5th
6th
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data 1 Read/Reset 3 Auto Select Program Unlock Bypass Unlock Bypass Program Unlock Bypass Reset Chip Erase Block Erase Erase Suspend Erase Resume Read CFI Query 3 4 3 2 2 6 6+ 1 1 1 AAA AAA AAA AAA X X AAA AAA X X AA AA AA AA AA A0 90 AA AA B0 30 98 555 555 555 555 PA X 555 555 55 55 55 55 PD 00 55 55 AAA AAA 80 80 AAA AAA AA AA 555 555 55 55 AAA BA 10 30 X AAA AAA AAA F0 90 A0 20 PA PD X F0
1. X Don't Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal. The Command Interface only uses A-1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A18, DQ8DQ14 and DQ15 are Don't Care. DQ15A-1 is A-1 when BYTE is VIL or DQ15 when BYTE is VIH.
Table 6.
Program, Erase times and Program, Erase Endurance cycles
Parameter Min Typ(1)(2) 12 0.8 30 10 12 6 100,000 20 200(3) 60(3) 30(3) Max(2) 60(3) 6
(4)
Unit s s s s s s cycles years
Chip Erase Block Erase (64 Kbytes) Erase Suspend Latency time Program (Byte or Word) Chip Program (Byte by Byte) Chip Program (Word by Word) Program/Erase cycles (per Block) Data Retention
1. Typical values measured at room temperature and nominal voltages. 2. Sampled, but not 100% tested. 3. Maximum value measured at worst case conditions for both temperature and VCC after 100,00 program/erase cycles. 4. Maximum value measured at worst case conditions for both temperature and VCC.
21/53
Status Register
M29F800DT
5
Status Register
Bus Read operations from any address always read the Status Register during Program and Erase operations. It is also read during Erase Suspend when an address within a block being erased is accessed. The bits in the Status Register are summarized in Table 7: Status Register Bits.
5.0.1
Data Polling Bit (DQ7)
The Data Polling Bit can be used to identify whether the Program/Erase Controller has successfully completed its operation or if it has responded to an Erase Suspend. The Data Polling Bit is output on DQ7 when the Status Register is read. During Program operations the Data Polling Bit outputs the complement of the bit being programmed to DQ7. After successful completion of the Program operation the memory returns to Read mode and Bus Read operations from the address just programmed output DQ7, not its complement. During Erase operations the Data Polling Bit outputs '0', the complement of the erased state of DQ7. After successful completion of the Erase operation the memory returns to Read Mode. In Erase Suspend mode the Data Polling Bit will output a '1' during a Bus Read operation within a block being erased. The Data Polling Bit will change from a '0' to a '1' when the Program/Erase Controller has suspended the Erase operation. Figure 6: Data Polling flowchart, gives an example of how to use the Data Polling Bit. A Valid Address is the address being programmed or an address within the block being erased.
5.0.2
Toggle Bit (DQ6)
The Toggle Bit can be used to identify whether the Program/Erase Controller has successfully completed its operation or if it has responded to an Erase Suspend. The Toggle Bit is output on DQ6 when the Status Register is read. During Program and Erase operations the Toggle Bit changes from '0' to '1' to '0', etc., with successive Bus Read operations at any address. After successful completion of the operation the memory returns to Read mode. During Erase Suspend mode the Toggle Bit will output when addressing a cell within a block being erased. The Toggle Bit will stop toggling when the Program/Erase Controller has suspended the Erase operation. If any attempt is made to erase a protected block, the operation is aborted, no error is signalled and DQ6 toggles for approximately 100s. If any attempt is made to program a protected block or a suspended block, the operation is aborted, no error is signalled and DQ6 toggles for approximately 1s. Figure 7: Data Toggle flowchart, gives an example of how to use the Data Toggle Bit.
22/53
M29F800DT
Status Register
5.0.3
Error Bit (DQ5)
The Error Bit can be used to identify errors detected by the Program/Erase Controller. The Error Bit is set to '1' when a Program, Block Erase or Chip Erase operation fails to write the correct data to the memory. If the Error Bit is set a Read/Reset command must be issued before other commands are issued. The Error bit is output on DQ5 when the Status Register is read. Note that the Program command cannot change a bit set to '0' back to '1' and attempting to do so will set DQ5 to `1'. A Bus Read operation to that address will show the bit is still `0'. One of the Erase commands must be used to set all the bits in a block or in the whole memory from '0' to '1'
5.0.4
Erase Timer Bit (DQ3)
The Erase Timer Bit can be used to identify the start of Program/Erase Controller operation during a Block Erase command. Once the Program/Erase Controller starts erasing the Erase Timer Bit is set to '1'. Before the Program/Erase Controller starts the Erase Timer Bit is set to '0' and additional blocks to be erased may be written to the Command Interface. The Erase Timer Bit is output on DQ3 when the Status Register is read.
5.0.5
Alternative Toggle Bit (DQ2)
The Alternative Toggle Bit can be used to monitor the Program/Erase controller during Erase operations. The Alternative Toggle Bit is output on DQ2 when the Status Register is read. During Chip Erase and Block Erase operations the Toggle Bit changes from '0' to '1' to '0', etc., with successive Bus Read operations from addresses within the blocks being erased. A protected block is treated the same as a block not being erased. Once the operation completes the memory returns to Read mode. During Erase Suspend the Alternative Toggle Bit changes from '0' to '1' to '0', etc. with successive Bus Read operations from addresses within the blocks being erased. Bus Read operations to addresses within blocks not being erased will output the memory cell data as if in Read mode. After an Erase operation that causes the Error Bit to be set the Alternative Toggle Bit can be used to identify which block or blocks have caused the error. The Alternative Toggle Bit changes from '0' to '1' to '0', etc. with successive Bus Read Operations from addresses within blocks that have not erased correctly. The Alternative Toggle Bit does not change if the addressed block has erased correctly.
23/53
Status Register Table 7. Status Register Bits(1)
Address Any address Any address Any address Any address Erasing Block Non-Erasing Block Erasing Block Block Erase Non-Erasing Block Erasing Block Erase Suspend Non-Erasing Block Good Block address Erase Error Faulty Block address
1. Unspecified data bits should be ignored.
M29F800DT
Operation Program Program during Erase Suspend Program Error Chip Erase Block Erase before timeout
DQ7 DQ7 DQ7 DQ7 0 0 0 0 0 1
DQ6 Toggle Toggle Toggle Toggle Toggle Toggle Toggle Toggle No Toggle
DQ5 0 0 1 0 0 0 0 0 0
DQ3 - - - 1 0 0 1 1 -
DQ2 - - - Toggle Toggle No Toggle Toggle No Toggle Toggle
RB 0 0 0 0 0 0 0 0 1 1
Data read as normal 0 0 Toggle Toggle 1 1 1 1 No Toggle Toggle
0 0
Figure 6.
Data Polling flowchart
START
READ DQ5 & DQ7 at VALID ADDRESS
DQ7 = DATA NO NO
YES
DQ5 =1 YES
READ DQ7 at VALID ADDRESS
DQ7 = DATA NO FAIL
YES
PASS
AI03598
24/53
M29F800DT Figure 7. Data Toggle flowchart
Status Register
START READ DQ6
READ DQ5 & DQ6
DQ6 = TOGGLE YES NO
NO
DQ5 =1 YES READ DQ6 TWICE
DQ6 = TOGGLE YES FAIL
NO
PASS
AI01370C
25/53
Maximum rating
M29F800DT
6
Maximum rating
Stressing the device above the rating listed in the Absolute Maximum Ratings" table may cause permanent damage to the device. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 8.
Symbol TBIAS TSTG VIO VCC VID
Absolute maximum ratings
Parameter Temperature under bias Storage temperature Input or Output Supply voltage Identification voltage voltage(1)(2) Min -50 -65 -0.6 -0.6 -0.6 Max 125 150 VCC +0.6 6 13.5 Unit C C V V V
1. Minimum voltage may undershoot to -2V during transition and for less than 20ns during transitions. 2. Maximum voltage may overshoot to VCC +2V during transition and for less than 20ns during transitions.
26/53
M29F800DT
DC and AC parameters
7
DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table 9: Operating and AC measurement conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 9. Operating and AC measurement conditions
M29F800D Parameter Min VCC Supply voltage Ambient Operating Temperature (range 1) Ambient Operating Temperature (range 6) Load capacitance (CL) Input Rise and Fall times Input Pulse voltages Input and Output Timing Ref. voltages 0 to 3 1.5 4.5 0 -40 30 10 55 Max 5.5 70 85 Min 4.5 0 -40 100 10 0.45 to 2.4 0.8 and 2.0 70/ 90 Max 5.5 70 85 V C C pF ns V V Unit
Figure 8.
AC measurement I/O waveform
High Speed (55ns) 3V 1.5V 0V
Standard (70, 90ns) 2.4V 2.0V 0.8V
AI05276
0.45V
27/53
DC and AC parameters Figure 9. AC measurement Load Circuit
1.3V VCC
M29F800DT
1N914
3.3k DEVICE UNDER TEST CL 0.1F
OUT
CL includes JIG capacitance
AI05277
Table 10.
Symbol CIN COUT
Device capacitance(1)
Parameter Input capacitance Output capacitance Test Condition VIN = 0V VOUT = 0V Min Max 6 12 Unit pF pF
1. Sampled only, not 100% tested.
28/53
M29F800DT Table 11.
Symbol ILI ILO ICC1 ICC2 ICC3 ICC4
(1)
DC and AC parameters DC characteristics
Parameter Test condition 0V VIN VCC 0V VOUT VCC E = VIL, G = VIH, f = 6MHz E = VIH E = VCC 0.2V, RP = VCC 0.2V Program/Erase Controller active -0.5 2 IOL = 5.8mA IOH = -2.5mA 2.4 11.5 A9 = VID 3.2 12.5 100 4.2 Min Max 1 1 20 2 150 20 0.8 VCC + 0.5 0.45 Unit
A A
Input Leakage Current Output Leakage Current Supply Current (Read) Supply Current (Standby) TTL Supply Current (Standby) CMOS Supply Current (Program/Erase) Input Low voltage Input High voltage Output Low voltage Output High voltage TTL CMOS Identification voltage Identification Current Program/Erase Lockout Supply voltage
mA mA
A
mA V V V V V
A
VIL VIH VOL VOH VID IID VLKO
V
1. Sampled only, not 100% tested.
Figure 10. Read Mode AC waveforms
tAVAV A0-A18/ A-1 tAVQV E tELQV tELQX G tGLQX tGLQV DQ0-DQ7/ DQ8-DQ15 tBHQV BYTE tELBL/tELBH tBLQZ
AI06154
VALID tAXQX
tEHQX tEHQZ
tGHQX tGHQZ VALID
29/53
DC and AC parameters Table 12.
Symbol tAVAV tAVQV tELQX(1) tELQV tGLQX(1) tGLQV tEHQZ(1) tGHQZ(1) tEHQX tGHQX tAXQX tELBL tELBH tBLQZ tBHQV
M29F800DT
Read AC characteristics
M29F800D Alt tRC tACC tLZ tCE tOLZ tOE tHZ tDF tOH tELFL tELFH tFLQZ tFHQV Parameter Address Valid to Next Address Valid Address Valid to Output Valid Chip Enable Low to Output Transition Chip Enable Low to Output Valid Output Enable Low to Output Transition Output Enable Low to Output Valid Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Chip Enable, Output Enable or Address Transition to Output Transition Chip Enable to BYTE Low or High BYTE Low to Output Hi-Z BYTE High to Output Valid Test condition 55 E = VIL, G = VIL E = VIL, G = VIL G = VIL G = VIL E = VIL E = VIL G = VIL E = VIL Min Max Min Max Min Max Max Max Min Max Max Max 55 55 0 55 0 30 18 18 0 5 25 30 70/ 90 70 70 0 70 0 30 20 20 0 5 30 40 ns ns ns ns ns ns ns ns ns ns ns ns Unit
1. Sampled only, not 100% tested.
30/53
M29F800DT Figure 11. Write AC waveforms, Write Enable controlled
tAVAV A0-A18/ A-1 VALID tWLAX tAVWL E tELWL G tGHWL W tWLWH
DC and AC parameters
tWHEH
tWHGL
tWHWL tDVWH DQ0-DQ7/ DQ8-DQ15 VALID tWHDX
VCC tVCHEL RB tWHRL
AI06155
31/53
DC and AC parameters Table 13.
Symbol tAVAV tELWL tWLWH tDVWH tWHDX tWHEH tWHWL tAVWL tWLAX tGHWL tWHGL tWHRL
(1)
M29F800DT
Write AC characteristics, Write Enable controlled
M29F800D Alt tWC tCS tWP tDS tDH tCH tWPH tAS tAH Parameter 55 Address Valid to Next Address Valid Chip Enable Low to Write Enable Low Write Enable Low to Write Enable High Input Valid to Write Enable High Write Enable High to Input Transition Write Enable High to Chip Enable High Write Enable High to Write Enable Low Address Valid to Write Enable Low Write Enable Low to Address Transition Output Enable High to Write Enable Low tOEH tBUSY tVCS Write Enable High to Output Enable Low Program/Erase Valid to RB Low VCC High to Chip Enable Low Min Min Min Min Min Min Min Min Min Min Min Max Min 55 0 45 45 0 0 20 0 45 0 0 30 50 70/ 90 70 0 45 45 0 0 20 0 45 0 0 30 50 ns ns ns ns ns ns ns ns ns ns ns ns s Unit
tVCHEL
1. Sampled only, not 100% tested.
Figure 12. Write AC waveforms, Chip Enable controlled
tAVAV A0-A18/ A-1 VALID tELAX tAVEL W tWLEL G tGHEL E tEHEL tDVEH DQ0-DQ7/ DQ8-DQ15 VALID tEHDX tELEH tEHGL tEHWH
VCC tVCHWL RB tEHRL
AI06156
32/53
M29F800DT Table 14.
Symbol tAVAV tWLEL tELEH tDVEH tEHDX tEHWH tEHEL tAVEL tELAX tGHEL tEHGL tEHRL(1) tVCHWL tOEH tBUSY tVCS
DC and AC parameters Write AC characteristics, Chip Enable controlled
M29F800D Alt tWC tWS tCP tDS tDH tWH tCPH tAS tAH Parameter 55 Address Valid to Next Address Valid Write Enable Low to Chip Enable Low Chip Enable Low to Chip Enable High Input Valid to Chip Enable High Chip Enable High to Input Transition Chip Enable High to Write Enable High Chip Enable High to Chip Enable Low Address Valid to Chip Enable Low Chip Enable Low to Address Transition Output Enable High Chip Enable Low Chip Enable High to Output Enable Low Program/Erase Valid to RB Low VCC High to Write Enable Low Min Min Min Min Min Min Min Min Min Min Min Max Min 55 0 45 45 0 0 20 0 45 0 0 30 50 70/ 90 70 0 45 45 0 0 20 0 45 0 0 30 50 ns ns ns ns ns ns ns ns ns ns ns ns s Unit
1. Sampled only, not 100% tested.
Figure 13. Reset/Block Temporary Unprotect AC waveforms
W, E, G tPHWL, tPHEL, tPHGL RB tRHWL, tRHEL, tRHGL RP tPLPX tPHPHH tPLYH
AI06870
33/53
DC and AC parameters Table 15.
Symbol tPHWL(1) tPHEL tPHGL(1) tRHWL(1) tRHEL(1) tRHGL(1) tPLPX tPLYH(1) tPHPHH(1)
M29F800DT Reset/Block Temporary Unprotect AC characteristics
M29F800D Alt Parameter 55 tRH RP High to Write Enable Low, Chip Enable Low, Output Enable Low RB High to Write Enable Low, Chip Enable Low, Output Enable Low RP Pulse Width RP Low to Read Mode RP Rise Time to VID Min 50 70/ 90 50 ns Unit
tRB tRP tREADY tVIDR
Min Min Max Min
0 500 10 500
0 500 10 500
ns ns s ns
1. Sampled only, not 100% tested.
34/53
M29F800DT
Package mechanical
8
Package mechanical
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect . The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
35/53
Package mechanical
M29F800DT
Figure 14. SO44 - 44 lead Plastic Small Outline, 525 mils body width, package outline
A2 b e D
A C CP
N
E
EH
1
A1
L
SO-d
1. Drawing is not to scale.
Table 16.
SO44 - 44 lead Plastic Small Outline, 525 mils body width, package mechanical data
millimeters inches Max 2.80 0.10 2.30 0.40 0.15 2.20 0.35 0.10 2.40 0.50 0.20 0.08 28.20 13.30 16.00 1.27 0.80 8 44 44 28.00 13.20 15.75 - 28.40 13.50 16.25 - 1.1102 0.5236 0.6299 0.0500 0.0315 8 1.1024 0.5197 0.6201 - 0.0906 0.0157 0.0059 0.0039 0.0866 0.0138 0.0039 0.0945 0.0197 0.0079 0.0030 1.1181 0.5315 0.6398 - Typ Min Max 0.1102
Symbol Typ A A1 A2 b C CP D E EH e L N Min
36/53
M29F800DT
Package mechanical Figure 15. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, package outline
1
48
e
D1
B
24
25
L1 A2 A
E1 E
DIE
A1 C CP
L
TSOP-G
1. Drawing is not to scale.
Table 17.
TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, package mechanical data
millimeters inches Max 1.200 0.100 1.000 0.220 0.050 0.950 0.170 0.100 0.150 1.050 0.270 0.210 0.080 12.000 20.000 18.400 0.500 0.600 0.800 3 0 5 11.900 19.800 18.300 - 0.500 12.100 20.200 18.500 - 0.700 0.4724 0.7874 0.7244 0.0197 0.0236 0.0315 3 0 5 0.4685 0.7795 0.7205 - 0.0197 0.0039 0.0394 0.0087 0.0020 0.0374 0.0067 0.0039 Typ Min Max 0.0472 0.0059 0.0413 0.0106 0.0083 0.0031 0.4764 0.7953 0.7283 - 0.0276
Symbol Typ A A1 A2 B C CP D1 E E1 e L L1 Min
37/53
Part numbering
M29F800DT
9
Part numbering
Table 18.
Example:
Ordering information scheme
M29 F 800DB
55 N
6
T
Device Type M29
Operating Voltage F = VCC = 5V 10% Device Function 800D = 8 Mbit (x8/x16), Boot Block
Array Matrix T = Top Boot B = Bottom Boot
Speed 55 = 55 ns 70 = 70 ns 90 = 90 ns
Package M = SO44 N = TSOP48: 12 x 20 mm
Temperature Range 1 = 0 to 70 C 6 = -40 to 85 C
Option E = ECOPACK(R) package, standard package F = ECOPACK(R) package, tape & reel 24mm packing
38/53
M29F800DT
Part numbering Devices are shipped from the factory with the memory content bits erased to '1'. For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.
39/53
Block address table
M29F800DT
Appendix A
Table 19.
# 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
T
Block address table
Top Boot Block addresses, M29F800D
Size (Kbytes) 16 8 8 32 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 Address range (x8) FC000h-FFFFFh FA000h-FBFFFh F8000h-F9FFFh F0000h-F7FFFh E0000h-EFFFFh D0000h-DFFFFh C0000h-CFFFFh B0000h-BFFFFh A0000h-AFFFFh 90000h-9FFFFh 80000h-8FFFFh 70000h-7FFFFh 60000h-6FFFFh 50000h-5FFFFh 40000h-4FFFFh 30000h-3FFFFh 20000h-2FFFFh 10000h-1FFFFh 00000h-0FFFFh Address range (x16) 7E000h-7FFFFh 7D000h-7DFFFh 7C000h-7CFFFh 78000h-7BFFFh 70000h-77FFFh 68000h-6FFFFh 60000h-67FFFh 58000h-5FFFFh 50000h-57FFFh 48000h-4FFFFh 40000h-47FFFh 38000h-3FFFFh 30000h-37FFFh 28000h-2FFFFh 20000h-27FFFh 18000h-1FFFFh 10000h-17FFFh 08000h-0FFFFh 00000h-07FFFh
40/53
M29F800DT Table 20.
# 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Block address table Bottom Boot Block addresses, M29F800DB
Size (Kbytes) 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 32 8 8 16 Address range (x8) F0000h-FFFFFh E0000h-EFFFFh D0000h-DFFFFh C0000h-CFFFFh B0000h-BFFFFh A0000h-AFFFFh 90000h-9FFFFh 80000h-8FFFFh 70000h-7FFFFh 60000h-6FFFFh 50000h-5FFFFh 40000h-4FFFFh 30000h-3FFFFh 20000h-2FFFFh 10000h-1FFFFh 08000h-0FFFFh 06000h-07FFFh 04000h-05FFFh 00000h-03FFFh Address range (x16) 78000h-7FFFFh 70000h-77FFFh 68000h-6FFFFh 60000h-67FFFh 58000h-5FFFFh 50000h-57FFFh 48000h-4FFFFh 40000h-47FFFh 38000h-3FFFFh 30000h-37FFFh 28000h-2FFFFh 20000h-27FFFh 18000h-1FFFFh 10000h-17FFFh 08000h-0FFFFh 04000h-07FFFh 03000h-03FFFh 02000h-02FFFh 00000h-01FFFh
41/53
Common Flash Interface (CFI)
M29F800DT
Appendix B
Common Flash Interface (CFI)
The Common Flash Interface is a JEDEC approved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when necessary. When the CFI Query Command is issued the device enters CFI Query mode and the data structure is read from the memory. Table 21, Table 22, Table 23, Table 24, Table 25, and Table 26 show the addresses used to retrieve the data. The CFI data structure also contains a security area where a 64 bit unique security number is written (see Table 26: Security Code Area). This area can be accessed only in Read mode by the final user. It is impossible to change the security number after it has been written by ST. Issue a Read command to return to Read mode. Table 21. Query structure overview(1)
Sub-section name x16 10h 1Bh 27h 40h 61h x8 20h 36h 4Eh 80h C2h CFI Query Identification String Command set ID and algorithm data offset System Interface Information Device Geometry Definition Primary Algorithm-specific Extended Query table Security Code Area Device timing & voltage information Flash device layout Additional information specific to the Primary Algorithm (optional) 64 bit unique device number Description
Address
1. Query data are always presented on the lowest order data outputs.
42/53
M29F800DT Table 22.
Address Data x16 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah x8 20h 22h 24h 26h 28h 2Ah 2Ch 2Eh 30h 32h 34h 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h Query Unique ASCII String "QRY" Description
Common Flash Interface (CFI) CFI Query Identification String(1)
Value "Q" "R" "Y" Primary Algorithm Command Set and Control Interface ID code 16 bit ID code defining a specific algorithm Address for Primary Algorithm extended Query table (see Table 24) Alternate Vendor Command Set and Control Interface ID Code second vendor - specified algorithm supported Address for Alternate Algorithm extended Query table AMD Compatible P = 40h
NA
NA
1. Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are `0'.
Table 23.
Address
CFI Query System Interface Information
Data Description Value
x16
x8 VCC Logic Supply Minimum Program/Erase voltage 0045h bit 7 to 4BCD value in volts bit 3 to 0BCD value in 100 mV VCC Logic Supply Maximum Program/Erase voltage 0055h bit 7 to 4BCD value in volts bit 3 to 0BCD value in 100 mV 0000h VPP [Programming] Supply Minimum Program/Erase voltage 0000h VPP [Programming] Supply Maximum Program/Erase voltage 0004h Typical timeout per single byte/word program = 2 s 0000h Typical timeout for minimum size write buffer program = 000Ah Typical timeout per individual block erase = 2n ms 0000h Typical timeout for full chip erase = 2n ms 2n s
n
1Bh
36h
4.5V
1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h
38h 3Ah 3Ch 3Eh 40h 42h 44h 46h 48h 4Ah 4Ch
5.5V NA NA 16s NA 1s see note(1) 256s NA 8s see note(1)
0004h Maximum timeout for byte/word program = 2n times typical 0000h Maximum timeout for write buffer program = 2 times typical 0003h Maximum timeout per individual block erase = 2n times typical 0000h Maximum timeout for chip erase = 2 times typical
n n
1. Not supported in the CFI
43/53
Common Flash Interface (CFI) Table 24.
Address Data x16 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch x8 4Eh 50h 52h 54h 56h 58h 5Ah 5Ch 5Eh 60h 62h 64h 66h 68h 6Ah 6Ch 6Eh 70h 72h 74h 76h 78h 0014h 0002h 0000h 0000h 0000h 0004h 0000h 0000h 0040h 0000h 0001h 0000h 0020h 0000h 0000h 0000h 0080h 0000h 000Eh 0000h 0000h 0001h Device Size = 2n in number of bytes Flash Device Interface Code description Description
M29F800DT
Device Geometry Definition
Value 1 MByte x8, x16 Async. NA
Maximum number of bytes in multi-byte program or page = 2n Number of Erase Block Regions within the device. It specifies the number of regions within the device containing contiguous Erase Blocks of the same size. Region 1 Information Number of identical size erase block = 0000h+1 Region 1 Information Block size in Region 1 = 0040h * 256 byte Region 2 Information Number of identical size erase block = 0001h+1 Region 2 Information Block size in Region 2 = 0020h * 256 byte Region 3 Information Number of identical size erase block = 0000h+1 Region 3 Information Block size in Region 3 = 0080h * 256 byte Region 4 Information Number of identical-size erase block = 000Eh+1 Region 4 Information Block size in Region 4 = 0100h * 256 byte
4
1 16 Kbyte 2 8 Kbyte 1 32 Kbyte 15 64 Kbyte
44/53
M29F800DT Table 25.
Address Data x16 40h 41h 42h 43h 44h 45h x8 80h 82h 84h 86h 88h 8Ah 0050h Description
Common Flash Interface (CFI) Primary Algorithm-specific Extended Query table
Value "P" "R" "I" "1" "0" Yes
0052h Primary Algorithm Extended Query table unique ASCII string "PRI" 0049h 0031h Major version number, ASCII 0030h Minor version number, ASCII Address Sensitive Unlock (bits 1 to 0) 0000h 00 = required, 01= not required Silicon Revision Number (bits 7 to 2) 0002h 0001h 0001h 0004h Erase Suspend 00 = not supported, 01 = Read only, 02 = Read and Write Block Protection 00 = not supported, x = number of sectors in per group Temporary Block Unprotect 00 = not supported, 01 = supported Block Protect /Unprotect 04 = M29W400B
46h 47h 48h 49h 4Ah 4Bh 4Ch
8Ch 8Eh 90h 92h 94h 96h 98h
2 1 Yes 4 No No No
0000h Simultaneous Operations, 00 = not supported 0000h Burst Mode, 00 = not supported, 01 = supported 0000h Page Mode, 00 = not supported, 01 = 4 page word, 02 = 8 page word
Table 26.
Security Code Area
Data Description
Address x16 61h 62h 63h 64h x8 C3h, C2h C5h, C4h C7h, C6h C9h, C8h XXXX XXXX 64 bit: unique device number XXXX XXXX
45/53
Block protection
M29F800DT
Appendix C
Block protection
Block protection can be used to prevent any operation from modifying the data stored in the Flash. Each Block can be protected individually. Once protected, Program and Erase operations on the block fail to change the data. There are three techniques that can be used to control Block Protection, these are the Programmer technique, the In-System technique and Temporary Unprotection. Temporary Unprotection is controlled by the Reset/Block Temporary Unprotection pin, RP; this is described in the Signal Descriptions section. Unlike the Command Interface of the Program/Erase Controller, the techniques for protecting and unprotecting blocks change between different Flash memory suppliers. For example, the techniques for AMD parts will not work on STMicroelectronics parts. Care should be taken when changing drivers for one part to work on another.
9.1
Programmer technique
The Programmer technique uses high (VID) voltage levels on some of the bus pins. These cannot be achieved using a standard microprocessor bus, therefore the technique is recommended only for use in Programming Equipment. To protect a block follow the flowchart in Figure 16: Programmer Equipment Block Protect flowchart. To unprotect the whole chip it is necessary to protect all of the blocks first, then all blocks can be unprotected at the same time. To unprotect the chip follow Figure 17: Programmer Equipment Chip Unprotect flowchart. Table 27: Programmer technique bus operations, BYTE = VIH or VIL, gives a summary of each operation. The timing on these flowcharts is critical. Care should be taken to ensure that, where a pause is specified, it is followed as closely as possible. Do not abort the procedure before reaching the end. Chip Unprotect can take several seconds and a user message should be provided to show that the operation is progressing.
9.2
In-System technique
The In-System technique requires a high voltage level on the Reset/Blocks Temporary Unprotect pin, RP. This can be achieved without violating the maximum ratings of the components on the microprocessor bus, therefore this technique is suitable for use after the Flash has been fitted to the system. To protect a block follow the flowchart in Figure 18: In-System Equipment Block Protect flowchart. To unprotect the whole chip it is necessary to protect all of the blocks first, then all the blocks can be unprotected at the same time. To unprotect the chip follow Figure 19: InSystem Equipment Chip Unprotect flowchart. The timing on these flowcharts is critical. Care should be taken to ensure that, where a pause is specified, it is followed as closely as possible. Do not allow the microprocessor to service interrupts that will upset the timing and do not abort the procedure before reaching the end. Chip Unprotect can take several seconds and a user message should be provided to show that the operation is progressing.
46/53
M29F800DT Table 27. Programmer technique bus operations, BYTE = VIH or VIL
E G W Address Inputs A0-A18 A9 = VID, A12-A18 Block address Others = X A9 = VID, A12 = VIH, A15 = VIH Others = X A0 = VIL, A1 = VIH, A6 = VIL, A9 = VID, A12-A18 Block address Others = X A0 = VIL, A1 = VIH, A6 = VIH, A9 = VID, A12-A18 Block address Others = X
Block protection
Operation
Data Inputs/Outputs DQ15A-1, DQ14-DQ0 X X Pass = XX01h Retry = XX00h Retry = XX01h Pass = XX00h
Block Protect Chip Unprotect Block Protection verify Block Unprotection verify
VIL
VID
VIL Pulse VIL Pulse
VID VID
VIL
VIL
VIH
VIL
VIL
VIH
47/53
Block protection Figure 16. Programmer Equipment Block Protect flowchart
START
M29F800DT
ADDRESS = BLOCK ADDRESS Set-up W = VIH n=0
G, A9 = VID, E = VIL
Wait 4s Protect W = VIL Wait 100s W = VIH E, G = VIH, A0, A6 = VIL, A1 = VIH E = VIL Wait 4s G = VIL Wait 60ns Read DATA
Verify
DATA NO = 01h YES A9 = VIH E, G = VIH End PASS ++n = 25 YES A9 = VIH E, G = VIH FAIL
AI03469
NO
48/53
M29F800DT Figure 17. Programmer Equipment Chip Unprotect flowchart
START PROTECT ALL BLOCKS Set-up n=0 CURRENT BLOCK = 0
Block protection
A6, A12, A15 = VIH(1) E, G, A9 = VID
Wait 4s Unprotect W = VIL Wait 10ms W = VIH E, G = VIH
ADDRESS = CURRENT BLOCK ADDRESS A0 = VIL, A1, A6 = VIH
E = VIL Wait 4s G = VIL Verify Wait 60ns Read DATA
INCREMENT CURRENT BLOCK
NO
DATA = 00h
YES
NO
++n = 1000 YES
LAST BLOCK YES A9 = VIH E, G = VIH PASS
NO
End
A9 = VIH E, G = VIH FAIL
AI03470
49/53
Block protection Figure 18. In-System Equipment Block Protect flowchart
START Set-up n=0 RP = VID WRITE 60h ADDRESS = BLOCK ADDRESS A0 = VIL, A1 = VIH, A6 = VIL
M29F800DT
Protect
WRITE 60h ADDRESS = BLOCK ADDRESS A0 = VIL, A1 = VIH, A6 = VIL
Wait 100s WRITE 40h ADDRESS = BLOCK ADDRESS A0 = VIL, A1 = VIH, A6 = VIL Verify
Wait 4s READ DATA ADDRESS = BLOCK ADDRESS A0 = VIL, A1 = VIH, A6 = VIL
DATA NO = 01h YES RP = VIH End ISSUE READ/RESET COMMAND ++n = 25 YES RP = VIH ISSUE READ/RESET COMMAND NO
PASS
FAIL
AI03471
50/53
M29F800DT Figure 19. In-System Equipment Chip Unprotect flowchart
Block protection
START PROTECT ALL BLOCKS
Set-up
n=0 CURRENT BLOCK = 0
RP = VID WRITE 60h ANY ADDRESS WITH A0 = VIL, A1 = VIH, A6 = VIH
Unprotect
WRITE 60h ANY ADDRESS WITH A0 = VIL, A1 = VIH, A6 = VIH
Wait 10ms
WRITE 40h ADDRESS = CURRENT BLOCK ADDRESS A0 = VIL, A1 = VIH, A6 = VIH
Verify
Wait 4s READ DATA ADDRESS = CURRENT BLOCK ADDRESS A0 = VIL, A1 = VIH, A6 = VIH INCREMENT CURRENT BLOCK
NO
DATA = 00h
YES
NO
++n = 1000 YES RP = VIH
LAST BLOCK YES RP = VIH
NO
End
ISSUE READ/RESET COMMAND
ISSUE READ/RESET COMMAND
FAIL
PASS
AI03472
51/53
Revision history
M29F800DT
Revision history
Table 28.
Date 13-Dec-2001 21-Jan-2002
Document revision history
Revision -01 -02 First Issue VIH(max) value corrected Description of Ready/Busy signal clarified (and Figure 13: Reset/Block Temporary Unprotect AC waveforms modified) Clarified allowable commands during block erase Clarified the mode the device returns to in the CFI Read Query command section Revision numbering modified: a minor revision will be indicated by incrementing the digit after the dot, and a major revision, by incrementing the digit before the dot (revision version 03 equals 3.0). Erase Suspend Latency Time (typical) and Data Retention parameters added to Table 6: Program, Erase times and Program, Erase Endurance cycles, and notes added to the table. Figure 1: Logic diagram, and Figure 7: Data Toggle flowchart corrected. Lead-free package options E and F added to Table 18: Ordering information scheme. Document promoted to full datasheet. TSOP48 package information updated (see Figure 15: TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, package outline and Table 17: TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, package mechanical data). Cross-references updated in Appendix B: Common Flash Interface (CFI) on page 42. Temperature range 3 added. Changed document to new template; indicated that Ready/Busy Output now available for both SO44 and TSOP48 packages (see Table 1.: Signal names); removed temperature range 3 from Table 9 and Table 18; ecopack compliant Revision details
01-Mar-2002
-03
17-Feb-2003
4.0
08-Jul-2003
4.1
24-Aug-2006
5
52/53
M29F800DT
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST'S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER'S OWN RISK.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
(c) 2006 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
53/53

▲Up To Search▲

Price & Availability of M29F800DT06

	To Download M29F800DT06 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .